Palo Alto Networks

Santa Clara

Senior ASIC Design Engineer (NetSec)

FULL TIME ON-SITE SENIOR
Posted 16 days ago

Summary

Role Overview

Join the ASIC team to deliver digital logic for next-generation firewall platforms. You will own module design from specification through silicon bring-up, collaborating with verification and physical-design engineers. The goal is to meet aggressive performance, power, and schedule targets.

Key Responsibilities

  • Write clear design and micro-architecture specifications.
  • Design SystemVerilog RTL that meets area, performance, and power targets.
  • Verify your blocks using simulation, emulation, formal methods, and silicon bring-up.
  • Collaborate with verification engineers to debug complex scenarios and add design-for-debug features.
  • Partner with physical-design teams to review reports, rewrite RTL, and consult on floor-planning.
  • Innovate by piloting AI-driven design or verification flows to reduce schedule risk.

Requirements Snapshot

  • Possess a BS in EE, CE, or CS, with an MSEE or equivalent military experience preferred.
  • Have 10+ years of front-end ASIC design ownership, having shipped at least 2 chips to mass production.
  • Demonstrate solid experience with PCIe core integration and lab validation.
  • Exhibit expert SystemVerilog RTL skills.
  • Show scripting proficiency in Python, C/C++, Perl, bash, or tcsh.

Why Apply

  • Join a global cybersecurity leader known for challenging the security status quo.
  • Contribute to a mission that protects the digital age by preventing successful cyberattacks.
  • Work with a pioneering Security Operating Platform that drives continuous innovation and automation.

This summary was generated from the original job posting (AI-assisted, human-reviewed). For full details, visit the company's site.