Front End RTL Designer / SoC integration at Vertical Compute

The role

Vertical Compute is seeking a Front-End RTL Designer to build 3D-integrated chiplets for high-performance AI accelerators. You will lead top-level SoC integration and incorporate proprietary Vertical Integrated Memory technology to overcome industry bottlenecks.

What you'll do

• Lead top-level SoC and chiplet integration for AI accelerators
• Incorporate internal and third-party IPs into the chiplet design
• Integrate proprietary Vertical Integrated Memory technology with compute engines
• Partner with verification teams to build environments and debug RTL
• Collaborate with physical design teams to optimize PPA metrics
• Support synthesis and timing closure for the product

What you'll bring

• Degree in Electrical Engineering or a related technical field
• Experience in front-end RTL design and SoC integration
• Proficiency in SystemVerilog and Verilog languages
• Ability to optimize Power Performance and Area metrics
• Fluency in English with effective communication skills

Your impact

You will play a critical role in transforming breakthrough semiconductor physics into commercial reality by delivering cutting-edge AI accelerator solutions. Your work will directly demonstrate the potential of Vertical Integrated Memory technology, helping to solve global memory bottlenecks and power the next era of AI compute.