ASIC Physical Design Engineer, Library Characterization - Espoo

Job Description

At our Finland ASIC development centers in Oulu and Espoo, we develop ASICs for Bosch in consumer and industrial sensing applications. Your primary responsibility will be the characterization of standard cell and custom cell libraries, generating the latest library formats with cutting-edge tools and methodologies. You will also apply this expertise to support the physical implementation of digital subsystems within Mixed-Signal and System-on-chip ASICs.

• Create something new: You work in interdisciplinary teams, developing timing, power, and noise libraries for standard and custom cells, including at near-threshold voltages, utilizing the latest statistical library formats. Your expertise in analog circuit behaviour is crucial for accurate characterization.
• Reliable implementation: You ensure "First Time Right" IC Designs by delivering high-quality, validated library models, collaborating closely with analog, digital, and physical design teams.
• Think holistically: You understand design requirements, block-level specifications, and circuit documentation to perform comprehensive library characterization, and provide expert guidance on library usage for physical design.
• Networked communication: You are part of an international and globally distributed team, continuously improving our library characterization methodology.
• Observe and apply: You leverage your understanding of physical design flows (P&R, STA) to effectively integrate characterized libraries and ensure manufacturability for advanced process nodes.

Qualifications

Qualifications:

• Personality: High level of enthusiasm, creativity, and willingness to work in international and interdisciplinary teams.
• Working Practice: Effective team player with focused and independent working style.
• Experience: Proven industry experience with a focus on ASIC physical design and library characterization.
  • High expertise in library characterization, including LVF libraries and LVF-based timing sign-off.
  • Understanding of analog circuit principles and Spice circuit simulations for characterization.
  • Experience with modern ASIC technology, including near-threshold design challenges.
  • Proficiency with Cadence Liberate or Synopsys SiliconSmart, and STA tools like Synopsys PrimeTime or Cadence Tempus.
  • Solid understanding of logic backend tools (P&R, timing analysis, low power techniques).
  • Strong scripting and automation skills (Make based flow, Python, TCL, json, jinja 2, etc.).
• Languages: Proficient English language skills.
• Education: Degree (M.Sc., B.Sc.) of electrical engineering or equivalent with outstanding results.

Additional Information

We offer:

An exciting job at an international company who is working at the forefront of technology. Being a part of the Finnish department, you can become a part of the future!