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ALTEN

Munich

Digital Design Engineer Semiconductor (all gender)

FULL TIME ON-SITE MID
Posted about 1 month ago
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Summary

Role Overview

This role involves the design and verification of digital functionality using SystemVerilog, including adapting and enhancing existing IP modules. The position requires expertise in logic synthesis, implementation verification, and power simulations.

Key Responsibilities

  • Develop SystemVerilog code for digital functionality.
  • Adapt and enhance existing IP modules for new features.
  • Set up and execute logic synthesis with constraint management.
  • Perform implementation verification using Spyglass and LEC.
  • Conduct power simulations and analyze results.
  • Prepare comprehensive design documentation.

Requirements Snapshot

  • Degree in Electrical Engineering, Computer Science, Physics, or similar.
  • Proven experience in RTL design and verification (SystemVerilog, VHDL).
  • Strong background in logic synthesis, timing analysis, and power simulation.
  • Experience with industry-standard tools (Spyglass, DesignCompiler, LEC, Xcelium, ATPG).
  • Good communication skills in English.

Expected Impact

The successful candidate will contribute to the development and verification of robust digital designs, ensuring functionality, performance, and power efficiency of IP modules.

Why Apply

  • Opportunity for career development through Talent Management.
  • Enjoy a good work-life balance with flexible working hours and mobile working options.
  • Benefit from a comprehensive package of corporate benefits and perks.

This summary was generated from the original job posting (AI-assisted, human-reviewed). For full details, visit the company's site.

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